1. Field of the Invention
The present invention relates to techniques of restricting a time for using a specific resource by a master device.
2. Related Art
When a resource is shared by a plurality of master devices that are implemented on one or more LSIs (Large Scale Integration), there may be a need to have one master device use the resource without delay as much as possible upon a resource use request, while ensuring that another master device can use the resource a predetermined number of times per predetermined time period.
One example of such cases is explained below. A DMA (Direct Memory Access) controller and a processor as master devices share a memory as a resource. The DMA controller reads video data from the memory, and the read video data is sequentially played back by a playback device. The processor reads control data and the like from the memory, and controls a system using the read control data and the like.
To sequentially play back the video data while reading it, the DMA controller needs to be ensured of a predetermined number of memory accesses per predetermined time period. Meanwhile, to realize display screen switching controls and the like of high user responsiveness, the processor, which exercises such controls, needs to be allowed to access the memory without delay as much as possible.
In this case, a certain limit may need to be put on a time for which the processor occupies the memory resource, i.e. the number of memory accesses by the processor, in order to ensure the predetermined number of memory accesses for the DMA controller.
As one example of such resource use time restriction techniques, Japanese patent application publication No. 2005-258867 discloses a technique of restricting, when a plurality of devices (hereafter called “bus masters”) are connected to a memory bus, the number of memory accesses by a bus master, to thereby arbitrate between access requests from the plurality of bus masters.
The following explains an arbitration device disclosed in Japanese patent application publication No. 2005-258867.
To arbitrate for memory access between a bus master (hereafter called a “first master”) that needs to be ensured of a fixed number of accesses per predetermined transfer cycle (e.g. 63.6 μs) and a bus master (hereafter called a “second master”) whose access delay needs to be minimized while ensuring the fixed number of accesses for the first master, the arbitration device defines a maximum number of accesses the second master is permitted per predetermined transfer cycle, and priorities of the bus masters.
Suppose, in the case where five memory accesses are possible per predetermined transfer cycle, it is necessary to ensure the first master of three accesses per transfer cycle. This being the case, the arbitration device sets the maximum number of accesses the second master is permitted to perform per transfer cycle to two, and assigns a higher priority to the second master than the first master in order to minimize an access delay of the second master.
When an access request by the first master and an access request by the second master conflict with each other, the arbitration device prioritizes the second master in access permission, under a condition that the number of accesses by the second master within the current transfer cycle is smaller than the maximum number of permitted accesses (two). If the number of accesses by the second master within the current transfer cycle is the maximum number of permitted accesses (two), the arbitration device prohibits the second master from access.
In more detail, a remaining number of accesses the second master is permitted in each transfer cycle is set in an access counter internal to the arbitration device. Each time the second master is permitted to perform access, the access counter is decreased by 1. At the beginning of each transfer cycle, the access counter is reset to the maximum number of accesses the second master is permitted (two).
When an access request by the first master and an access request by the second master conflict with each other, the arbitration device permits the second master to perform access if the access counter is larger than 0, and prohibits the second master to perform access and permits the first master to perform access if the access counter is 0.
In this way, the arbitration device can reduce an access delay of the second master by prioritizing the second master, and also ensure the fixed number of accesses per transfer cycle for the first master by restricting the number of accesses the second master is permitted per transfer cycle.
However, this conventional technique can encounter the following problem. The beginning of an initial transfer cycle in the first master is determined based on a time at which the first master accesses the memory for the first time. However, there may be a case where this beginning of the transfer cycle is unknown to the arbitration device due to a reason such as the arbitration device having not been informed of the beginning by the first master.
In such a case, the timing of resetting the access counter in the arbitration device may not coincide with the beginning of each transfer cycle in the first master. When this occurs, the arbitration device will end up failing to appropriately restrict the number of accesses by the second master.
One example of this is explained below, with reference to FIG. 9.
FIG. 9 shows an example result of arbitrating between memory access requests from the first master and the second master by the arbitration device disclosed in Japanese patent application publication No. 2005-258867.
In this example, five memory accesses are possible per transfer cycle, the number of accesses ensured for the first master per transfer cycle is three, and the maximum number of accesses the second master is permitted per transfer cycle is two.
In FIG. 9, a timer 901 shows a value of a timer internal to the arbitration device. The timer is initially set to 4, and decreased by 1 each time a clock is received. When the timer reaches 0, it is reset to the initial value “4”. A transfer cycle 902 shows a transfer cycle in the first master and the second master, where one transfer cycle is made up of time slices 1 to 5.
In this example, the beginning of each transfer cycle is unknown to the arbitration device, and accordingly the timing of resetting the timer 901 (when the timer 901 is 4) does not coincide with the beginning of the transfer cycle 902 (when the transfer cycle 902 is 1), as shown in FIG. 9.
A first master 903 shows whether or not an access request is made by the first master and whether or not the access request is permitted. In FIG. 9, a mark “I” denotes a state where the first master does not request access, a mark “A” denotes a state where the first master requests access and the access is permitted, and a mark “W” denotes a state where the first master requests access and the access is not permitted.
A second master 904 shows whether or not an access request is made by the second master and whether or not the access request is permitted. The meanings of the marks “I”, “A”, and “W” are the same as those in the first master 903. An access counter 905 shows a remaining number of accesses the second master is permitted per transfer cycle.
A case where three memory accesses can be ensured for the first master is explained first.
T1 and T2 indicate times at which only the first master requests access. At T1 and T2, the arbitration device permits the first master to access the memory.
T3 indicates a time at which the first master and the second master request access. At T3, the access counter 905 is “2” which is larger than “0”, and so the arbitration device permits the second master to access the memory, and the access counter 905 is decreased by 1 to “1”.
T4 indicates a time at which the first master and the second master request access, as with T3. At T4, the access counter 905 is “1” which is larger than “0”, and so the arbitration device permits the second master to access the memory, and the access counter 905 is decreased by 1 to “0”.
T5 indicates a time at which only the first master requests access. At T5, the arbitration device permits the first master to access the memory.
Thus, in the transfer cycle of T1 to T5, the access delay by the second master can be reduced while ensuring three accesses for the first master per transfer cycle.
A case where three memory accesses cannot be ensured for the first master is explained next.
T7 and T8 indicate times at which the first master and the second master request access. At T6, the timer 901 is reset to the initial value “4”, and the access counter 905 is reset to the initial value “2”. At T7 and T8, the access counter 905 is larger than “0”, and so the arbitration device permits the second master to access the memory, and the access counter 905 is decreased by 1 to “0”.
T9 indicates a time at which the timer 901 is reset to the initial value “4” and the access counter 905 is reset to the initial value “2”. At T9 and T10, the first master and the second master request access, as with T7 and T8. At T9 and T10, the access counter 905 is larger than “0”, and so the arbitration device permits the second master to access the memory.
T11 indicates a time at which only the first master requests access. At T11, the arbitration device permits the first master to access the memory.
Thus, in the transfer cycle of T7 to T11, though the access delay by the second master is reduced, three accesses per transfer cycle cannot be ensured for the first master.